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1 ? fn6719.0 ISL94201 multi-cell li-ion ba ttery pack analog front-end the ISL94201 is an analog front end for a microcontroller in a multi-cell li-ion battery pack. the ISL94201 supports battery pack configurations consisting of 4-cells to 7-cells in series and 1 or more cells in parallel. the ISL94201 provides an internal 3.3v voltage regulator, and cell voltage monitor level shifters. using an internal analog multiplexer the ISL94201 provides monitoring of each cell voltage plus internal and external temperature by a separate microcontroller with an a/d converter. software on this microcontroller implements all battery pack control functionality. features ? four battery-backed software controlled flags ? 10% accurate 3.3v voltage regulator (minimum 25ma out with external npn transistor having current gain of 70) ? monitored cell voltage output stable in 100s ?simple i 2 c host interface ? sleep operation with programmable negative edge or positive edge wake-up ? <10a sleep mode ? pb-free (rohs compliant) applications ? power tools ? battery backup systems ?e-bikes ? portable test equipment ? medical systems ? hybrid vehicle ? military electronics pinout ISL94201 (24 ld qfn) top view ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL94201irz 942 01irtz 24 ld 4x4 qfn l24.4x4d note: these intersil pb-free pl astic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. scl sda wkup rgc rgo temp3v vcell3 vcell2 vcell1 vss vss vss nc vc7/vcc vcell6 vcell5 nc vcell4 tempi ao nc nc nc vss 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 data sheet july 3, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6719.0 july 3, 2008 functional diagram 3.3vdc regulator vss vc7/vcc sda vcell6 vcell5 vcell4 rgo vcell3 ao vcell2 vcell1 temp3v scl registers rgc wkup power control mux 7 backup supply control logic level shifters cell voltages osc temperature sensor, int/ext comparator ext temp enable tempi i 2 c i/f 2 pin descriptions symbol description vc7/vcc battery cell 7 voltage input/vcc supply. this pin is used to monitor the voltage of this ba ttery cell externally at pin ao. this pin also provides the operating voltage for the ic circuitry. vcelln battery cell n voltage input. this pin is used to monitor the voltage of this battery cell externally at pin ao. vcelln connects to the positive terminal of celln and the negative terminal of celln + 1. vss ground. this pin connects to the most negative terminal in the battery string. ao analog multiplexer output. the analog output pin is used by an external microcon troller to monitor the cell voltages and temperature sensor voltages. the microcontroller selects the specific voltage being applied to the output by writing to a control register. temp3v temperature monitor output control. this pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. the thermistor is located in close proximity to the cells. the temp3v output is connected internally to the rgo vol tage through a pmos switch only during a measurement of the temperatur e, otherwise the temp3v output is off. the temp3v output can be turned on continuously with a special control bit. microcontroller wake up control. tempi temperature monitor input. this pin inputs the voltage across a thermistor to det ermine the temperature of the cells. when this input drops below temp3v/13, an external over-temperature condition exis ts. the tempi voltage is also fed to the ao output pin throug h an analog multiplexer so the temperature of the cells can be monitored by the microcontroller. rgo regulated output voltage. this pin connects to the emitter of an external npn transistor and works in conjunction with the rgc pin to provides a regulated 3.3v. the voltage at this pin provides feedback for the regulator and power for many of the ISL94201int ernal circuits as well as providing the 3.3v output voltag e for the microcontroller and other external circuits. rgc regulated output control. this pin connects to the base of an external npn transistor and works in conjunction with the rgo pin to provide a regulated 3.3v. the rgc output provides the control si gnal for the external transistor to provide the 3.3v regulated voltage on the rgo pin. wkup wake up voltage. this input wakes up the part when the voltage cros ses a turn-on threshold (wake up is edge triggered). the condition of the pin is reflected in the wk up bit (the wkup bit is level sensitive.) wkpol bit = ?1?: the device wakes up on the rising edge of the wk up pin. also, the wkup bit is high only when the wkup pin voltage > threshold. wkpol bit = ?0?, the device wakes up on the falling edge of the wk up pin. also, the wkup bit is high only when the wkup pin voltage < threshold. sda serial data. this is the bidirectional data line for an i 2 c interface. scl serial clock. this is the clock input for an i 2 c communication link. ISL94201
3 fn6719.0 july 3, 2008 absolute maximum rati ngs thermal information power supply voltage, vcc . . . . . . . . . .v ss - 0.5v to v ss + 36.0v cell voltage, vcell vcelln - (vcelln - 1), vcell1 - vss . . . . . . . . . . . -0.5v to 5v terminal voltage, v term1 (scl, sda, tempi, rgo, ao, temp3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.5 to v rgo + 0.5v terminal voltage, v term3 (wkup) . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.5v to v cc (v cc <27v) terminal voltage, v term4 (rgc) . . . . . . . . . . . . . v ss - 0.5v to 5v terminal voltage, v term5 , (all other pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss - 0.5v to v cc +0.5v thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . 32 2 continuous package power dissipation . . . . . . . . . . . . . . . . .400mw storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . 5v to 10v operating voltage: vcc pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2v to 30.1v vcell1 - vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 4.3v vcelln - (vcelln-1) . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 4.3v caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating specifications over the recommended operating conditi ons unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits es tablished by characterization and are not production tested parameter symbol test condition min typ max unit operating voltage v cc 9.2 30.1 v power-up condition 1 v porvcc v cc voltage (note 3) 4 9.2 v power-up condition 2 threshold v por123 v cell1 - v ss and v cell2 - v cell1 and v cell3 - v cell2 (rising) (note 3) 1.1 1.7 2.3 v power-up condition 2 hysteresis v porhys v cell1 - v ss and v cell2 - v cell1 and v cell3 - v cell2 (falling) (note 3) 70 mv 3.3v regulated voltage v rgo 0a < i rgc < 350a 3.0 3.3 3.6 v 3.3vdc voltage regulator control current limit i rgc (control current at output of rgc. recommend npn with gain of 70+) 0.35 0.50 ma v cc supply current i vcc1 power-up defaults, wkup pin = 0v. 400 510 a rgo supply current i rgo1 power-up defaults, wkup pin = 0v. 300 410 a v cc supply current i vcc2 ldmonen bit = 1, wkpol bit = 1, vwkup = 10v, [ao3:ao0] bits = 03h. 500 700 a rgo supply current i rgo2 ldmonen bit = 1, wkpol bit = 1, vwkup = 10v, [ao3:ao0] bits = 03h. 450 650 a v cc supply current i vcc3 default register settings, except sleep bit = 1. wkup pin = vcell1 10 a rgo supply current i rgo3 default register settings, except sleep bit = 1. wkup pin = vcell1 1a vcell input current (v cell1 )i vcell1 ao3:ao0 bits = 0000h 14 a vcell input current (v celln )i vcelln ao3:ao0 bits = 0000h 10 a ISL94201
4 fn6719.0 july 3, 2008 over-temperature protection specifications internal temperature shutdown threshold t intsd 125 c internal temperature hysteresis t hys temperature drop needed to restore operation after over-temperature shutdown. 20 c internal over-temperature turn on delay time t itd 128 ms external temperature output current i xt current output capability at temp3v pin 1.2 ma external temperature limit threshold t xtf voltage at v tempi ; relative to falling edge -20 0 +20 mv external temperature limit hysteresis t xth voltage at v tempi . 60 110 160 mv external temperature monitor delay t xtd delay between activating the external sensor and the internal over-temperature detection. 1ms external temperature autoscan on-time t xtaon temp3v is on (3.3v) 5 ms external temperature autoscan off-time t xtaoff temp3v output is off. 635 ms analog output specifications cell monitor analog output voltage accuracy v aoc [v celln - (v celln-1 )]/2 - ao -15 4 30 mv cell monitor analog output external temperature accuracy v aoxt external temperature monitoring accuracy. voltage error at ao when monitoring tempi voltage (measured with tempi = 1v) -10 10 mv internal temperature monitor output voltage slope v intmon internal temperature monitor voltage change -3.5 mv/c internal temperature monitor output t int25 output at +25c 1.31 v ao output stabilization time t vsc from scl falling edge at data bit 0 of command to ao output stable within 0.5% of final value. ao voltage steps from 0v to 2v. (c ao = 10pf) (note 7) 0.1 ms wake up/sleep specifications device wkup pin voltage threshold (wkup pin active high - rising edge) v wkup1 wkup pin rising edge (wkpol = 1) device wakes up and sets wkup flag high. 3.5 5.0 6.5 v device wkup pi n hysteresis (wkup pin active high) v wkup1h wkup pin falling edge hysteresis (wkpol = 1) sets wkup flag low (does not automatically enter sleep mode) 100 mv input resistance on wkup r wkup resistance from wkup pin to vss (wkpol = 1) 130 230 330 k device wkup pin active voltage threshold (wkup pin active low - falling edge) v wkup2 wkup pin falling edge (wkpol = 0) device wakes up and sets wkup flag high. v cell1 -2.6 v cell1 -2.0 v cell1 -1.2 v operating specifications over the recommended operating conditi ons unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits es tablished by characterization and are not production tested (continued) parameter symbol test condition min typ max unit v temp3v 13 ------------------------------ ISL94201
5 fn6719.0 july 3, 2008 device wkup pi n hysteresis (wkup pin active low) v wkup2h wkup pin rising edge hysteresis (wkpol = 0) sets wkup flag low (does not automatically enter sleep mode). 200 mv device wake-up delay t wkup delay after voltage on wkup pin crosses the threshold (rising or falling) before activating the wkup bit. 20 40 60 ms serial interface characteristics scl clock frequency f scl 100 khz pulse width suppression time at sda and scl inputs t in any pulse narrower than the max spec is suppressed. 50 ns scl falling edge to sda output data valid t aa from scl falling crossing v ih (min), until sda exits the v il (max) to v ih (min) window. 3.5 s time the bus must be free before start of new transmission t buf sda crossing v ih (min) during a stop condition to sda crossing v ih (min) during the following start condition. 4.7 s clock low time t low measured at the v il (max) crossing. 4.7 s clock high time t high measured at the v ih (min) crossing. 4.0 s start condition setup time t su:sta scl rising edge to sda falling edge. both crossing the v ih (min) level. 4.7 s start condition hold time t hd:sta from sda falling edge crossing v il (max) to scl falling edge crossing v ih (min). 4.0 s input data setup time t su:dat from sda exiting the v il (max) to v ih (min) window to scl rising edge crossing v il (min). 250 ns input data hold time t hd:dat from scl falling edge crossing v ih (min) to sda entering the v il (max) to v ih (min) window. 300 s stop condition setup time t su:sto from scl rising edge crossing v ih (min) to sda rising edge crossing v il (max). 4.0 s stop condition hold time t hd:sto from sda rising edge to scl falling edge. both crossing v ih (min). 4.0 s data output hold time t dh from scl falling edge crossing v il (max) until sda enters the v il (max) to v ih (min) window. (note 4) 0ns sda and scl rise time t r from v il (max) to v ih (min). 1000 ns sda and scl fall time t f from v ih (min) to v il (max). 300 ns capacitive loading of sda or scl (note 5) cb total on-chip and off-chip 400 pf sda and scl bus pull-up resistor- off-chip (note 5) r out maximum is determined by t r and t f . for c b = 400pf, max is about 2k ~ 2.5k for c b = 40pf, max is about 15k to 20k 1k input leakage current (scl, sda) i li -10 10 a input buffer low voltage (scl, sda) v il voltage relative to v ss of the device. -0.3 v rgo x 0.3 v operating specifications over the recommended operating conditi ons unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits es tablished by characterization and are not production tested (continued) parameter symbol test condition min typ max unit ISL94201
6 fn6719.0 july 3, 2008 ISL94201 wake up timing (wkpol = 0) wake up timing (wkpol = 1) change in voltage source input buffer high voltage (scl, sda) v ih voltage relative to v ss of the device. v rgo x 0.7 v rgo +0.1 v output buffer low voltage (sda) v ol i ol = 1ma 0.4 v sda and scl input buffer hysteresis (note 5) i 2 chyst sleep bit = 0 0.05 * v rgo v notes: 3. power-up of the device requires all v cell1 , v cell2 , v cell3 , and vcc to be above the limits specified. 4. the device provides an internal hold time of at least 300ns for the sda signal to bridge the unidentified region of the falli ng edge of scl. 5. limits should be considered typi cal and are not production tested. 6. typical 5 2 , based on characterization data. 7. maximum output capacitance = 15pf. operating specifications over the recommended operating conditi ons unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise spec ified. temperature limits es tablished by characterization and are not production tested (continued) parameter symbol test condition min typ max unit v wkup2 v wkup2h t wkup t wkup 7 fn6719.0 july 3, 2008 automatic temperature scan serial interface timing diagrams bus timing symbol table auto temp control (internal activation) temp3v pin tmp3v/13 delay time = 1ms 635ms monitor time = 5ms 3.3v xot bit external over-temperature delay time = 1ms monitor temp during this high impedance time period threshold temperature t su:sto t high t su:sta t hd:sta t hd:dat t su:dat scl t f t low t buf t r t dh t aa sda (input timing) sda (output timing) waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance waveform inputs outputs ISL94201
8 fn6719.0 july 3, 2008 registers status registers table 1. registers addr register read/write 7 6 5 4 3 2 1 0 00h config/op status read only reserved reserved sa single afe wkup wkup pin status reserved reserved reserved reserved 01h operating status (note 10) read only reserved reserved xot ext over temp iot int over te m p reserved reserved reserved reserved 02h not used read/write reserved reserved reserved reserved reserved reserved reserved reserved 03h analog out read/write uflg1 user flag 1 uflg0 user flag 0 reserved reserved ao3 ao2 ao1 ao0 analog output select bits 04h control read/write sleep force sleep (note 11) reserved reserved reserved reserved reserved reserved reserved 05h not used read/write reserved reserved reserved reserved reserved reserved reserved reserved 06h not used read/write reserved reserved reserved reserved reserved reserved reserved reserved 07h feature set read/write (write only if fseten bit set) atmpoff turn off automatic external temp scan dis3 disable 3.3v reg. (device requires external 3.3v) tmp3on turn on temp3v reserved reserved por force por diswkup disable wkup pin wkpol wake up polarity 08h write enable read/write fseten enable feature set writes reserved reserved uflg3 user flag 3 uflg2 user flag 2 reserved reserved reserved 09h:ffh reserved na reserved notes: 8. a ?1? written to a control or configuration bit causes the acti on to be taken. a ?1? read from a status bit indicates that th e condition exists. 9. ?reserved? indicates that the bit or regi ster is reserved for future expansion. when writing to addresses 2, 3, 4, and 8: wri te a reserved bit with the value ?0?. do not write to reserved registers at addresses 09h through ffh. ignore reserved bits that are returned in a rea d operation. 10. these status bits are automatically cleared when the register is read. all other status bits are cleared when the condition is cleared. 11. this sleep bit is cleared on initial power up, by the wkup pin going high (when wkpol = ?1?) or by the wkup pin going low (whe n wkpol = ?0?), and by writing a ?0? to the location with an i 2 c command. table 2. config/op status register (addr: 00h) bit function description 7 reserved reserved for future expansion. 6 reserved reserved for future expansion. 5sa single afe indicates the device is an ISL94201. this bit is set in the chip and cannot be changed. 4 wkup wakeup pin status this bit is set and reset by hardware. when ?wkpol? is high: ?wkup? high = wkup pin > threshold voltage ?wkup? low = wkup pin < threshold voltage when ?wkpol? is low: ?wkup? high = wkup pin < threshold voltage ?wkup? low = wkup pin > threshold voltage 3 reserved reserved for future expansion. ISL94201
9 fn6719.0 july 3, 2008 control registers 2 reserved reserved for future expansion. 1 reserved reserved for future expansion. 0 reserved reserved for future expansion. table 2. config/op status register (addr: 00h) (continued) bit function description table 3. operating status register (addr: 01h) bit function description 7 reserved reserved for future expansion. 6 reserved reserved for future expansion. 5xot ext over-temp this bit is set to ?1? when the external thermistor indicates an over-temperature condition. if the temperature condition has cleared, this bit is reset when the register is read. 4iot int over-temp this bit is set to ?1? when the internal thermistor indica tes an over-temperature condition. if the temperature condition has cleared, this bit is rese t when the register is read. 3 reserved reserved for future expansion. 2 reserved reserved for future expansion. 1 reserved reserved for future expansion. 0 reserved reserved for future expansion. table 4. analog out control register (addr: 03h) bits function description 7uflg1 user flag 1 general purpose flag usable by mi crocontroller software. this bit is battery backed up, even when rgo turns off. 6uflg0 user flag 0 general purpose flag usable by mi crocontroller software. this bit is battery backed up, even when rgo turns off. 5:4 reserved reserved for future expansion bit 3 ao3 bit 2 ao2 bit 1 ao1 bit 0 ao0 output voltage 0 0 0 0 no output (low power state) 0001v cell1 0010v cell2 0011v cell3 0100v cell4 0101v cell5 0110v cell6 0111v cell7 1 0 0 0 external temperature 1 0 0 1 internal temperature 1 x 1 x reserved 1 1 x x reserved ISL94201
10 fn6719.0 july 3, 2008 configuration registers the device is configured fo r specific application requirements using the conf iguration registers. the configuration registers consist of sram memory. this memory is powered by the rgo output. in a sleep condition, an internal switch converts power for the contents of these registers from rgo to the vcell1 input. . table 5. control register (addr: 04h) bit function description 7 sleep force sleep setting this bit to ?1? forces the device to go into a sleep condition. this turns off the voltage regulator. the sleep bit is automatically reset to ?0? when the device wakes up. this bit does not reset the ao3:ao0 bits. 6:0 reserved reserved for future expansion. table 6. feature set configuration register (addr: 07h) bit function description 7 atmpoff turn off automatic external temp scan when set to ?1? this bit disables the automatic te mperature scan. when set to ?0?, the temperature is turned on for 5ms in every 640ms. 6dis3 disable 3.3v regulator setting this bit to ?1? disables t he internal 3.3v regulator. setting this bit to ?1? requires that there be an external 3.3v regulator connected to the rgo pin. 5tmp3on turn on temp 3.3v setting this bit to ?1? turns on the temp3v output to the external temperature sensor. the output will remain on as long as this bit remains ?1?. 4 reserved reserved for future expansion. 3 reserved reserved for future expansion. 2por force por setting this bit to ?1? forces a por condition. this resets all internal registers to zero. 1 diswkup disable wkup pin setting this bit to ?1? dis ables the wkup pin function. caution: setting this pin to ?1? prevents a wake up condition. if the device then goes to sleep, it cannot be waken without a communication link that resets this bit, or by power cycling the device. 0wkpol wake up polarity setting this bit to ?1? sets the device to wake up on a rising edge at the wkup pin. setting this bit to ?0? sets the device to wake up on a falling edge at the wkup pin. table 7. write enable register (addr: 08h) bit function description 7 fseten enable discharge set writes when set to ?1?, allows writes to the feature set regi ster. when set to ?0?, prevents writes to the feature set register (addr: 07h). default on initial power up is ?0?. 6 reserved reserved for future expansion. 5 reserved reserved for future expansion. 4uflg3 user flag 3 general purpose flag usable by microcontroller softwa re. this bit is battery backed up, even when rgo turns off. 3uflg2 user flag 3 general purpose flag usable by microcontroller softwa re. this bit is battery backed up, even when rgo turns off. 2 reserved reserved for future expansion. 1 reserved reserved for future expansion. 0 reserved reserved for future expansion. ISL94201
11 fn6719.0 july 3, 2008 device description design theory instructed by the microcontroll er, the ISL94201 performs cell voltage and temperature monitoring. battery connection the ISL94201supports packs of 5 to 7 series connected li-ion cells. connection guidelines for each cell combination are shown in figure 1. system power-up/power-down the ISL94201 powers up when the voltages on v cell1 , v cell2 , v cell3 and vcc all exceed their por threshold. at this time, the ISL94201 wakes up and turns on the rgo output. rgo provides a regulated 3.3vdc 10% voltage at pin rgo. it does this by using a control voltage on the rgc pin to drive an external npn tr ansistor (see figure 2.) the transistor should have a beta of at least 70 to provide ample current to the device and external circuits and should have a v ce of greater than 30v (preferably 50v). the voltage at the emitter of the npn transistor is monitored and regulated to 3.3v by the control signal rgc. rgo also powers most of the ISL94201internal circuits. a 500 resistor is recommended in the collector of the npn transistor to minimize initial current surge when the regulator turns on. once powered up, the device remains in a wake up state until put to sleep by the microcontroller (typically when the cells drop too low in voltage) or until the v cell1 , v cell2 , v cell3 or vcc voltages drop below their por threshold. wkup pin operation there are two ways to design a wake up of the ISL94201. in an active low connection (wkpol = ?0? - default), the device wakes up when a charger is connected to the pack. this pulls the wkup pin low when compared to a reference based on the v cell1 voltage. in an active high connection (wkpol = ?1?) the device wakes up when the wkup pin is pulled high by a connection through an external switch. vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 7 cells vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 6 cells vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 5 cells figure 1. battery connection options note: multiple cells can be connected in parallel vcell7 vcell6 vcell5 vcell4 vcell3 vcell2 vcell1 vss 4 cells rgc rgo vss vcc 3.3v gnd figure 2. voltage regulator circuits 500 ISL94201
12 fn6719.0 july 3, 2008 protection functions in the default recommended condition, the ISL94201automatically detects internal over-temperature, and external over-temperatur e conditions. the designer programs the microcontroller to respond to the over-temperature indications. over-temperature safety functions external temperature monitoring the external temperature is monitored by using a voltage divider consisting of a fixed resistor and a thermistor. this divider is powered by the ISL94201temp3v output. this output is normally controlled so it is on for only short periods to minimize current consumption. without microcontroller interven tion, and in the default state, the ISL94201provides an automat ic temperature scan. this scan circuit repeatedly turns on temp3v output (and the external temperature monitor) for 5ms out of every 640ms. in this way, the external temperature is monitored even if the microcontroller is asleep. when the temp3v output turns on, the ISL94201waits 1ms for the temperature reading to stabilize, then compares the external temperature voltage with an internal voltage divider that is set to temp3v/13. when the thermistor voltage is below the reference threshold after the delay, an external temperature fail condition exists. to set the external over-temperature limit, set the value of r x resistor to 12x the resistance of the thermistor at the over-temp threshold. the temp3v output pin also turns on when the microcontroller sets the ao3:ao0 bits to select that the external temperature voltage. this causes the tempi voltage to be placed on ao and activates (after 1ms) the over-temperature detection. as long as the ao3:ao0 bits point to the external temperature, the temp3v output remains on. because of the manual scan of the temperature, it may be desired to turn off the automatic scan, although they can be used at the same time without interference. to turn off the automatic scan, set the atmpoff bit. the microcontroller can over-ride both the automatic temperature scan and the microcontroller controlled temperature scan by setting t he temp3on configuration bit. this turns on the temp3v output to keep the temperature control voltage on all the time, for a continuous monitoring of an over-temperature condition. this likely will consume a significant amount of current, so this feature is usually used for special or test purposes. analog multiplexer selection the ISL94201devices can be used to externally monitor individual battery cell voltages and temperatures. each quantity can be monitored at the analog output pin (ao). the desired voltage is selected using the i 2 c interface and the ao3:ao0 bits. see figure 5. voltage monitoring since the voltage on each of the li-ion cells are normally higher than the regulated supp ly voltage, and since the voltages on the upper cells is much higher than is tolerated by a microcontroller, it is necessary to both level shift and divide the voltage before it can be monitored by the microcontroller or an external a/d converter. to get into the voltage range required by the external circuits, the voltage level shifter divides the cell voltage by 2 and references it to vss. therefore, a li-ion cell wit h a voltage of 4.2v becomes a voltage of 2.1v on the ao pin. temperature monitoring the voltage representing the ex ternal temperature applied at the tempi terminal is directed to the ao terminal through a mux, as selected by the ao control bits (see figures 4 and 5). the external temperature voltage is not divided by 2 as are the cell voltages. instead it is a direct reflection of the voltage at the tempi pin. a similar operation occurs when monitoring the internal temperature through the ao out put, except there is no external ?calibration? of the voltage associated with the internal temperature. for the internal temperature monitoring, the voltage at the ou tput is linear with respect to temperature. see ?operating specifications? for information about the output voltage at +25c and the output slope relative to temperature on page 4. ISL94201 figure 3. wake up control circuits vss 230k* * internal resistor only connected when wkpol=1. 5v wkup wkpol wkup (status) (control) wake up circuits v cell1 ISL94201
13 fn6719.0 july 3, 2008 user flags the ISL94201contains four flags in the register area that the microcontroller can use for general purpose indicators. these bits are designated uf lg3, uflg2, uflg1, and uflg0. the microcontroller can set or reset these bits by writing into the appropriate register. the user flag bits are battery backed up, so the contents remain even after exiting a sleep mode. however, if the microcontroller sets the por bit to force a power on reset, all of the user flags will also be reset. in addition, if the voltage on cell1 ever drops below the por voltage, the contents of the user flags (as well as all other register values) could be lost. serial interface interface conventions the device supports a bidirect ional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the ISL94201devices operate as slaves in all applications. when sending or receiving data, the convention is the most significant bit (msb) is sent firs t. so, the first address bit sent is bit 7. clock and data data states on the sda line can change only while scl is low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 6. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 7. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition is only issued afte r the transmitting device has released the bus. see figure 7. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, releases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge that it received the eight bits of data. see figure 8. ao rgo temp3v tempi vss i 2 c mux i 2 c temp monitor temp fail indicator figure 4. external temperature monitoring and control vss (on) registers tmp3on ao3:ao0 decode osc atmpoff 508ms 4ms to ? xot 12r r 1ms delay external ISL94201 ext temp r x ao vcell2 vss scl i 2 c figure 5. analog output monitoring diagram regs ao3:ao0 decode vcell1 vcell6 vc7/vcc sda 2 level shift level shift level shift level shift tempi int temp mux ext temp. mux ISL94201
14 fn6719.0 july 3, 2008 the device responds with an acknowledge after recognition of a start condition and the correct slave byte. if a write operation is selected, the device responds with an acknowledge after the receipt of each subsequent eight bits. the device acknowledges all incoming data and address bytes, except for the slave byte when the contents do not match the device?s internal slave address. in the read mode, the device transmits eight bits of data, releases the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continues to transmit data. the device terminates further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. . write operations for a write operation, the device requires a slave byte and an address byte. the slave by te specifies the particular device on the i 2 c bus that the master is writing to. the address specifies one of the r egisters in that device. after receipt of each byte, the device responds with an acknowledge, and awaits the next eight bits from the master. after the acknowledge, followin g the transfer of data, the master terminates the transfer by generating a stop condition. see figure 9. when receiving data from the master, the value in the data byte is transferred into the register specified by the address byte on the falling edge of the clock following the 8th data bit. after receiving the acknowledge after the data byte, the device automatically increm ents the address. so, before sending the stop bit, the mast er may send additional data to the device without re-sending t he slave and address bytes. after writing to address 0ah, the address ?wraps around? to address 0. do not continue to write to addresses higher than address 08h, since these add resses access registers that are reserved. writing to these locations can result in unexpected device operation. scl sda data stable data change data stable figure 6. valid data changes on i 2 c bus scl sda start stop figure 7. i 2 c start and stop bits 8 1 9 data output from transmitter data output from receiver start acknowledge figure 8. acknowledge response from receiver scl from master 0 0101 00 0 s t a r t s t o p slave byte register address data a c k a c k a c k sda bus signals from the slave signals from the master figure 9. write sequence ISL94201: slave byte = 50h ISL94201
15 fn6719.0 july 3, 2008 read operations read operations are initiated in the same manner as write operations with the host sending the address where the read is to start (but no data). then, the host sends an ack, a repeated start, and the slave byte with the lsb = 1. after the device acknowledges the slave byte, the device sends out one bit of data for each master clock. after the slave sends eight bits to the master, the master sends a nack (not acknowledge) to the device, to indicate the data transfer is complete, then the master sends a stop bit. see figure 10. after sending the eighth data bi t to the master, the device automatically increments its internal address pointer. so the master, instead of sending a nack and the stop bit, can send additional clocks to read the contents of the next register - without sending another slave and address byte. if the last address read or wr itten is known, the master can initiate a current address read. in this case, only the slave byte is sent before data is returned. see figure 10. . 1 0101 00 0 s t a r t s t o p slave byte data a c k n a c k figure 10. read sequence ISL94201: slave byte = 010100xh 0 0101 00 0 s t a r t slave byte register address a c k a c k sda bus signals from the slave signals from the master 1 0101 00 0 s t a r t s t o p slave byte data a c k n a c k random read current address read ISL94201
16 fn6719.0 july 3, 2008 register protection the feature set configuration re gister is write protected on initial power up. in order to write to these registers it is necessary to set a bit to enable each one. these write enable bits are in the write enable register (address 08h). write the fseten bit (addr 8:bit 7) to ?1? to enable changes to the data in the feature set register (address 7). the microcontroller can reset this bits back to zero to prevent inadvertent writes that change the operation of the pack. operation state machine figure 11 shows a device state machine which defines how the ISL94201responds to various conditions. power fails and one or more of the supplies, vcc, v cell1 , v cell2 , and v cell3 do not meet minimum voltage requirements wkup goes above or below threshold (edge triggered). or, sleep bit is set to ?0? i 2 c interface is disabled. biasing is disabled. all registers set to default values (all ?0?) power down state i 2 c interface is enabled. biasing is enabled. voltage regulator is enabled. power up state voltage regulator is on logic and registers are powered by rgo temperature monitor circuits are active (default). voltage and temperature monitoring circuits are awaiting external control. main operating state power is applied and all of the supplies, vcc, v cell1 , v cell2 , and v cell3 meet minimum voltage requirements voltage regulator is off biasing is off logic and registers are powered by v cell1 voltage and temperature monitoring circuits are off. i 2 c communication is active (if vcell1 voltage is high enough to operate with the external device.) sleep state sleep bit is set to ?1? figure 11. device operation state machine ISL94201
17 fn6719.0 july 3, 2008 applications circuits the following application circuits are ideas to consider when developing a battery pack implementation. there are many more ways that the pack can be designed. also refer to the isl9208 or isl9216 application guide for additional circuit design guidelines. figure 12. 7-cell application ci rcuit integrated charge/discharge vcell4 vcell1 vcell2 vcell3 vcell5 vcell6 ISL94201 vc7/vcc minimize length maximize gauge p- leds/ 1f resistors optional chrg scl sda wkup rgo rgc temp3v tempi therm ao p+ 1.8m 1.2m 500 0.1? 4.7f f reset a/d input v cc i/o gp i/o scl sda vss 200k 100 ISL94201
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6719.0 july 3, 2008 chrg figure 13. 7-cell application circuit with switch wake-up v ss vcell4 vcell1 vcell2 vcell3 vcell5 vcell6 ISL94201 vc7/vcc minimize length maximize gauge p- f reset a/d input v cc i/o gp leds 1f i/o resistors optional sw 825k scl sda wkup rgo rgc temp3v tempi therm ao scl sda 100 10v 0.1f 4.7f 500 ISL94201
19 fn6719.0 july 3, 2008 ISL94201 package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 50 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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